1. Field
Aspects herein are directed to phase lock loop systems and methods involving circuitry with optimal operation ranges, improved performance at process corners, and/or reduced sensitivity to jitter.
2. Description of Related Information
Phase locked loop (PLL) circuits are widely used as clock generators for a variety of applications including microprocessors, wireless devices, serial link transceivers, and disk drive electronics, among others. FIG. 1 illustrates a block diagram of a typical charge-pump based PLL circuit design, including a Phase Frequency Detector (PFD) 108, Charge Pump (CP) 112, Loop Filter (LPF) 116, Voltage Control Oscillator (VCO) 120, and multiple Dividers 104, 128, 124.
Various existing phase lock loop circuits may be configured with a VCO that generates an output clock that is frequency-locked and phase aligned with the input clock by virtue of a negative feedback loop. According to such circuitry, the output clock frequency will be defined by the following equation when PLL is in lock condition:CKOUT=CKIN*(N/M)*(1/P)
Further, in such embodiments, a typical VCO operates in a certain frequency range that will determine the PLL operating frequency range. The frequency of the VCO is controlled by Vcnt, the input voltage to the VCO. FIG. 2A shows a typical input voltage Vcnt versus VCO frequency, V-F curve. This VCO V-F curve will vary for different process corners. For example, for a slow process corner 224, the VCO frequency may be lower for the same Vcnt voltage. And for a fast process corner 228, the VCO frequency may be higher for the same Vcnt voltage. In other words, to maintain the same output frequency, a slow corner will require a higher Vcnt, and a fast corner will require a lower Vcnt. Moreover, there is a limited operating voltage range for Vcnt which is defined by the Vcnt(min) and the Vcnt(max). Therefore, it is very important to keep Vcnt within its operating voltage range for any process corner.
The frequency limit, freq_max 212, is highest frequency that VCO can generate, and the minimum frequency, freq_min 216, is the lowest frequency VCO can generate. As such, the VCO gain of FIG. 2A, Kvco, may be given by the following equation:Kvco=ΔF/ΔV=(freq_max−freq_min)/(Vcnt_max−Vcnt_min)
If VCO gain (Kvco) is very large, then any small amount of change in input voltageVcnt will translate into a big frequency disturbance at the VCO output, which will eventually show as jitter at the final output clock, CKOUT. Therefore, it is undesirable to design a VCO with a Kvco value that is too large such as 232 in FIG. 2A. If a circuit's frequency range is not expansive enough to cover the required range of operating frequencies, then a designer will have to increase the VCO gain to have steeper V-F curve such that it can cover the much higher and/or lower operating frequencies.
Turning to illustrative operation of the implementations shown in FIG. 2A, FIG. 2B is a timing diagram illustrating input voltage Vcnt required for high frequency operation curve 236 and a low frequency operation curve 240. Here, an input voltage Vcnt 234 of a very high value (0.94 v) may be required, e.g. at 244, for the VCO to generate a high frequency clock output a at slow process corner. Conversely, an input voltage Vcnt of a very low value (0.12 v) may be required, e.g. at 248, for low frequency clock output at fast process corner. Such restrictions may severely push the headroom for the charge pump circuitry, and cause large current mismatch between charging current Ip and discharging current In. To avoid drawbacks such as the above-mentioned charge-pump current mismatch, it is desirable to keep the Vcnt operating near the middle range of power supply voltage (VDD) at any process corners.